Cerebras AI Wafer

Earlier attempts at wafer-scale integration had yield issues. Here the lithography-reticle-sized rectangles interconnect only with upper layer metal, and each has a local clock, so it’s almost like a wafer-scale multi-chip module.

It can can route around regional failures. This architecture is OK for AI and avoids earlier WSI shortcomings.

With 44GB of SRAM (6T cell, 1 ECC bit per byte), I calculate that approximately 60% of its 4 trillion transistors are for memory.

I took a short video pan across the surface